Improving Pipelined Soft Processors with Multithreading

Designers of FPGA-based systems are increasingly including soft processors-processors implemented in programmable logic-in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency...

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Bibliographic Details
Main Authors: Labrecque, Martin, Steffan, J. Gregory
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Field programmable gate arrays
Frequency
Instruction sets
Logic
Multithreading
Pipelines
Process design
System-on-a-chip
Yarn
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Summary:Designers of FPGA-based systems are increasingly including soft processors-processors implemented in programmable logic-in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency as the best metric with which to compare potential designs. In this paper we demonstrate that 3, 5, and 7-stage pipelined multithreaded soft processors are 33%, 77%, and 106% more area efficient than their single-threade counterparts, the result of careful tuning of the architecture, ISA, and number of threads.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2007.4380649