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Improving Pipelined Soft Processors with Multithreading
Designers of FPGA-based systems are increasingly including soft processors-processors implemented in programmable logic-in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency...
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| creator | Labrecque, Martin Steffan, J. Gregory |
| description | Designers of FPGA-based systems are increasingly including soft processors-processors implemented in programmable logic-in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency as the best metric with which to compare potential designs. In this paper we demonstrate that 3, 5, and 7-stage pipelined multithreaded soft processors are 33%, 77%, and 106% more area efficient than their single-threade counterparts, the result of careful tuning of the architecture, ISA, and number of threads. |
| doi_str_mv | 10.1109/FPL.2007.4380649 |
| format | conference_proceeding |
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Gregory</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore (Online service)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Labrecque, Martin</au><au>Steffan, J. Gregory</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Improving Pipelined Soft Processors with Multithreading</atitle><btitle>2007 International Conference on Field Programmable Logic and Applications</btitle><stitle>FPL</stitle><date>2007-08</date><risdate>2007</risdate><spage>210</spage><epage>215</epage><pages>210-215</pages><issn>1946-147X</issn><eissn>1946-1488</eissn><isbn>1424410592</isbn><isbn>9781424410590</isbn><eisbn>1424410606</eisbn><eisbn>9781424410606</eisbn><abstract>Designers of FPGA-based systems are increasingly including soft processors-processors implemented in programmable logic-in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency as the best metric with which to compare potential designs. In this paper we demonstrate that 3, 5, and 7-stage pipelined multithreaded soft processors are 33%, 77%, and 106% more area efficient than their single-threade counterparts, the result of careful tuning of the architecture, ISA, and number of threads.</abstract><pub>IEEE</pub><doi>10.1109/FPL.2007.4380649</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1946-147X |
| ispartof | 2007 International Conference on Field Programmable Logic and Applications, 2007, p.210-215 |
| issn | 1946-147X 1946-1488 |
| language | eng |
| recordid | cdi_ieee_primary_4380649 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Field programmable gate arrays Frequency Instruction sets Logic Multithreading Pipelines Process design System-on-a-chip Yarn |
| title | Improving Pipelined Soft Processors with Multithreading |
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