Soft IP Core Implementation of Recursive Least Squares Filter using Only Multplicative and Additive Operators

Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the sys...

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Bibliographic Details
Main Authors: Lightbody, Gaye, Woods, Roger, Francey, Jonathan
Format: Conference Proceeding
Language:English
Subjects:
Arithmetic
Circuits
Computer architecture
Field programmable gate arrays
Filtering
Filters
Least squares methods
Pipeline processing
Resonance light scattering
Throughput
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Summary:Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and addition, thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilinx Virtex 4 FPGA giving a 5 GFLOPS performance.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2007.4380725