An FPGA Based Memory Efficient Shared Buffer Implementation

This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derive...

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Bibliographic Details
Main Authors: Burns, Dwayne, Toal, Ciaran, McLaughlin, Kieran, Sezer, Sakir, Hutton, Mike, Cackovic, Kevin
Format: Conference Proceeding
Language:English
Subjects:
Delay
Field programmable gate arrays
Hardware
IP networks
Memory architecture
Quality of service
Random access memory
Scheduling algorithm
Telecommunication traffic
Time division multiplexing
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Description
Summary:This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8Gbps and is scalable up to 20Gbps.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2007.4380740