A 35-to-46-Gb/s Ultra-Low Jitter Clock and Data Recovery Circuit for Optical Fiber Transmission Systems

We demonstrated an ultra-low jitter clock and data recovery (CDR) circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture, which consists of a phase tracking loop and a fr...

Full description

Saved in:
Bibliographic Details
Main Authors: Noguchi, H., Hosoya, K., Ohhira, R., Uchida, H., Noda, A., Yoshida, N., Wada, S.
Format: Conference Proceeding
Language:English
Subjects:
Bit error rate
Circuit optimization
Clocks
Error-free operation
Frequency locked loops
Jitter
Optical fibers
Optical tuning
Signal processing
Tracking loops
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We demonstrated an ultra-low jitter clock and data recovery (CDR) circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture, which consists of a phase tracking loop and a frequency tracking loop. The CDR chip, which was made using an InP-HBT process, shows an extremely clear eye opening with an ultra-low jitter (< 9 mUI-rms) and an error-free operation (
ISSN:1550-8781
2374-8443
DOI:10.1109/CSICS07.2007.40