3D Capacitive Interconnections for High Speed Interchip Communication

A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 μ m CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with elect...

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Bibliographic Details
Main Authors: Canegallo, R., Fazzi, A., Ciccarelli, L., Magagni, L., Natali, F., Rolandi, P.L., Jung, E., Di Cioccio, L., Guerrieri, R.
Format: Conference Proceeding
Language:English
Subjects:
Assembly
Clocks
CMOS process
Coupling circuits
Electrodes
Energy consumption
Frequency
Integrated circuit interconnections
Propagation delay
Transmitters
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Summary:A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 μ m CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15×15 μm 2 a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit . In the asynchronous scheme we demonstrate with electrodes 8×8 μm 2 a vertical propagation of clock at 1.7GHz and a propagation delay of 420ps for general purpose signal with energy consumption of 80fJ/bit . Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 10 13 bits transmitted.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2007.4405670