A 2GHz, 7W (max) 64b PowerTM Microprocessor Core

The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7...

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Bibliographic Details
Main Authors: Murray, Daniel, Huang, Zhibin, Javarappa, Naveen, Kanapathipillai, Pradeep, Klass, Fabian, Liu, Fang, Mehta, Anup, Modukuru, Yamini, Nerurkar, Nishant, Radhakrishnan, Abhijit, Santhanam, Sribalan, Burnette, James, Sugisawa, Junji, Sundar, Shyam, Tam, Honkai John, Wen, Ricky, Wu, Eric, Yeh, Jung-Cheng, Yong, John, Zambare, Sanjay, Campbell, Brian, Chung, Mark, Fernandes, Bruce, Ghosh, Subhendra, Goel, Rajat, Hess, Greg, Huang, Hang
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS logic circuits
CMOS process
Energy consumption
Java
Logic circuits
Microprocessors
Out of order
Power dissipation
Testing
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Summary:The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2007.4405833