Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A

The modeling and simulation of an all-digital PLL is presented. Verilog-A, owing to its flexibility, is used to create both behavioral and gate-level models used in system-level and circuit-based simulation. The methodology presented allows us to simulate the PLL closed-loop and accurately take into...

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Bibliographic Details
Main Authors: Fergusson, W.W., Patel, R.H., Bereza, W.
Format: Conference Proceeding
Language:English
Subjects:
Charge pumps
Circuit noise
Circuit simulation
Hardware design languages
Low pass filters
Mathematical model
Noise figure
Phase locked loops
Phase noise
Quantization
Online Access:Request full text
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Description
Summary:The modeling and simulation of an all-digital PLL is presented. Verilog-A, owing to its flexibility, is used to create both behavioral and gate-level models used in system-level and circuit-based simulation. The methodology presented allows us to simulate the PLL closed-loop and accurately take into account reference phase noise, DCO phase noise, quantization noise and any excess of it, allowing us to validate our jitter budget for any given application.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2007.4405863