45nm High-k/Metal-Gate CMOS Technology for GPU/NPU Applications with Highest PFET Performance

• Main Authors: Huang, H.T., Liu, Y.C., Hou, Y.T., Chen, R.C.-J., Lee, C.H., Chao, Y.S., Hsu, P.F., Chen, C.L., Guo, W.H., Yang, W.C., Perng, T.H., Shen, J.J., Yasuda, Y., Goto, K., Chen, C.C., Huang, K.T., Chuang, H., Diaz, C.H., Liang, M.S.
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS process; CMOS technology; Degradation; Dielectric devices; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Random access memory; Surface-mount technology; Tellurium
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2007.4418924

Highest planar HK/MG PFET performance (I ON = 790 muA at I off = 100 nA, Vdd= 1 V and Lg= 33 nm) has been demonstrated with a gate-first dual-metal CMOS integrated process and proven by functional SRAM cell. Integrating modern stressors without IL re-growth and achieving band edge work function without increasing T INV are two major challenges for gate-first HK/MG processes. In this work, band-edge effective work function has been achieved without increasing T INV . Furthermore, with successful integration of stress techniques like SiGe-S/D, SMT and CESL, not only performance was improved by 30% but also no reliability degradation was observed. Finally, no degradation from decreasing poly-pitch also suggests its good scalability to next generations.