A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

• Main Authors: I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen, An-Yeu Wu
• Format: Conference Proceeding
• Language: English
• Subjects: Circuit noise; Circuit optimization; Circuit synthesis; Costs; Hardware; Interference; Markov random fields; Nanoscale devices; Noise level; Very large scale integration
• DOI: 10.1109/ASSCC.2007.4425694

As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov random field carry lookahead adder (MRF_CLA), in 0.13 mum CMOS process technology. The measurement results show that the proposed MRF_CLA can provide 24.5 dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1].