A 65nm Pure CMOS one-time programmable memory using a two-port antifuse cell implemented in a matrix structure

A pure CMOS one-time programmable (PCOP) memory using an antifuse is presented. PCOP memory adopts two-port cell architecture implemented in a matrix structure. This architecture achieves optimization of performance both for programming and reading. Furthermore, it solves the write disturb problem a...

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Bibliographic Details
Main Authors: Matsufuji, K., Namekawa, T., Nakano, H., Ito, H., Wada, O., Otsuka, N.
Format: Conference Proceeding
Language:English
Subjects:
Breakdown voltage
CMOS logic circuits
CMOS memory circuits
CMOS technology
Logic programming
MOSFETs
Parasitic capacitance
Redundancy
Temperature distribution
Testing
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Summary:A pure CMOS one-time programmable (PCOP) memory using an antifuse is presented. PCOP memory adopts two-port cell architecture implemented in a matrix structure. This architecture achieves optimization of performance both for programming and reading. Furthermore, it solves the write disturb problem and realizes pseudo "1" read test. An 8 Kbit macro is developed utilizing a 65 nm pure CMOS logic technology. The cell area and the macro size are 15.3 mum 2 and 0.244 mm 2 , respectively.
DOI:10.1109/ASSCC.2007.4425768