45nm/32nm CMOS ˜ Challenge and Perspective

Product of 45 nm node technology will start by the end of this year. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the usage of immersion lithography. Most of the other technologies used for 45 n...

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Bibliographic Details
Main Author: Ishimaru, K.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
CMOS technology
Collaboration
High K dielectric materials
High-K gate dielectrics
Insulation
Lithography
Logic devices
Metal-insulator structures
Random access memory
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Summary:Product of 45 nm node technology will start by the end of this year. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the usage of immersion lithography. Most of the other technologies used for 45 nm node are the extension of those used for 65 nm node. On the other hand, there will be a big jump for 32 nm node technology. The biggest item is metal gate and high-k gate insulator system. Self barrier layer formation for BEOL is also new item. To achieve the target performance, performance improvement for each component is required. Variability in not only SRAM but also in logic will increase. To overcome these difficulties, closer collaboration between device and circuit is important.
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2007.4430244