Variation tolerant high resolution and low latency time-to-digital converter

A high resolution time-to-digital converter (TDC) with low latency and low deadtime is proposed. A coarse time quantization derived from a differential inverter delay line is locally interpolated with passive voltage dividers. The high resolution TDC is monotonic by construction which makes the conc...

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Bibliographic Details
Main Authors: Henzler, S., Koeppe, S., Lorenz, D., Kamp, W., Kuenemund, R., Schmitt-Landsiedel, D.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
CMOS technology
Delay effects
Delay lines
Interpolation
Pulse width modulation inverters
Quantization
Signal resolution
Time measurement
Voltage
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Summary:A high resolution time-to-digital converter (TDC) with low latency and low deadtime is proposed. A coarse time quantization derived from a differential inverter delay line is locally interpolated with passive voltage dividers. The high resolution TDC is monotonic by construction which makes the concept very robust against process variations. The feasibility is demonstrated with an 8-bit TDC with a resolution of 0.25 inverter delays in a 90 nm low power CMOS technology. The resolution limits imposed by clock uncertainty and local variations are derived theoretically.
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2007.4430278