Continuous time digitizer utilizing multiphase sampling technique

In this paper, the new architecture of a high-speed continuous time digitizer is proposed. With the aid of a two-level multiphase sampling technique, the time digitizer can use only 16 delay cells and DFFs to perform the flash-type conversion of 64-stage interpolation. The time digitizer can obtain...

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Bibliographic Details
Main Authors: Chorng-Sii Hwang, Chin-Wei Sung, Hen-Wai Tsao
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Clocks
Delay effects
Delay lines
Frequency
Jitter
Sampling methods
Signal resolution
Time measurement
Timing
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Summary:In this paper, the new architecture of a high-speed continuous time digitizer is proposed. With the aid of a two-level multiphase sampling technique, the time digitizer can use only 16 delay cells and DFFs to perform the flash-type conversion of 64-stage interpolation. The time digitizer can obtain 78 ps resolution with a reference frequency running at 200 MHz. The continuous input clock frequency can be up to 250 MHz. The test chip is fabricated in TSMC 0.18 mum 1P6M mixed mode process. The layout area occupies 1.08 mm 2 . The DNL is within -0.62 ~ +0.51 and INL within -0.99 ~ +0.98. A novel clock multiplier is also introduced to provide multiphase generation with the frequency output range within 0.64 ~ 1.8 GHz.
ISSN:1082-3654
2577-0829
DOI:10.1109/NSSMIC.2007.4436352