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Data acquisition and control for the LCLS pixel array detector

A data Acquisition (DAQ) and control system is being developed for a pixel array detector that will be used for a single-particle scattering experiment at the linac coherent light source (LCLS). The experiment requires that sub-picosecond pulses of 8 kEV X-rays are scattered off single particles 120...

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Bibliographic Details
Main Authors: Hromalik, M.S., Philipp, H.T., Koerner, L.J., Tate, M.W., Gruner, S.M.
Format: Conference Proceeding
Language:English
Subjects:
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Description
Summary:A data Acquisition (DAQ) and control system is being developed for a pixel array detector that will be used for a single-particle scattering experiment at the linac coherent light source (LCLS). The experiment requires that sub-picosecond pulses of 8 kEV X-rays are scattered off single particles 120 times a second. The scattered X-rays are converted to charge in a 2-dimensional pixelated diode array. The charge is integrated on to the 760times760 pixel detector readout chip and digitized in-pixel. The full detector is composed of tiled 185times192 pixel readout chips. The DAQ and control system provides low-level control of the integration and read-out processes, sets the detector mode of operation, addresses the pixels and transfers the data to high-speed local storage. Low-level data processing such as reordering, frame formatting and data averaging may also be required before data transfer. The DAQ and Control system is designed in a hierarchical and modular manner using a Xilinx XC4V100FX FPGA based DAQ board and is user controlled and monitored in software using master/slave command handshaking across the PCI Express bus. This allows for a very customized yet interactive and flexible system while sustaining a data throughput to disk in excess of 1.1 Gbps. Full speed detector control and data acquisition have been achieved for a single module chip CMOS ASIC (192times185 pixels) using the system described. Simultaneous to data acquisition, the DAQ and control system will also provide low-latency data transfer to a remote massive storage system on 10 GbE.
ISSN:1082-3654
2577-0829
DOI:10.1109/NSSMIC.2007.4436498