Silicon evaluation of longest path avoidance testing for small delay defects

This work presents a silicon evaluation of testing for small-delay defects using an approach called longest path avoidance testing. The motivation for LPA testing is to improve outgoing product quality by identifying delay defects that escape critical path delay testing. Results from experiments run...

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Bibliographic Details
Main Authors: Turakhia, R., Daasch, W.R., Ward, M., Van Slyke, J.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Circuit faults
Circuit testing
Delay
Frequency
Integrated circuit testing
Logic testing
Production
Silicon
Timing
Online Access:Request full text
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Description
Summary:This work presents a silicon evaluation of testing for small-delay defects using an approach called longest path avoidance testing. The motivation for LPA testing is to improve outgoing product quality by identifying delay defects that escape critical path delay testing. Results from experiments run on high volume production 180 nm ASIC are quantified in terms of test escapes and reliability escapes. Techniques for modeling the impact of small-delay testing are discussed.
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2007.4437564