Eliminating uT induced memory fails through waferless auto clean

In this paper, micro trenching (muT) on silicon substrate caused by the poly gate etch process, was found to be the root cause of memory bin failures (MBIST) in our 0.15 mum devices. Through advanced FA techniques using CAFM (conductive atomic force microscopy) & nano probing, we found that the...

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Bibliographic Details
Main Authors: Goa Yee Boon, Teo, S., Au Hing Ho, Leong, D.
Format: Conference Proceeding
Language:English
Subjects:
Atomic force microscopy
Degradation
Etching
Failure analysis
Gold
Random access memory
Silicon
Testing
Transconductance
Vehicles
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Summary:In this paper, micro trenching (muT) on silicon substrate caused by the poly gate etch process, was found to be the root cause of memory bin failures (MBIST) in our 0.15 mum devices. Through advanced FA techniques using CAFM (conductive atomic force microscopy) & nano probing, we found that the micro trenching MBIST failures occurs primarily due abnormal leakage across the gate due gate oxide damage next to the micro trench. In severe cases transconductance degradation of the Pass gate (PG) transistor was observed. We discovered the micro trenching phenomena was due to 'cold' poly etcher chamber effect. A novel method by running Pre-WAC (waferless auto clean) using the O2 and SF6 gas before polysilicon etch was found to be effective in eliminating the fails.
ISSN:1523-553X
DOI:10.1109/ISSM.2007.4446895