An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning

VLSI floor-planning in the gigascale era must deal with multiple objectives including wiring congestion, performance and reliability. Genetic algorithms lend themselves naturally to multi-objective optimization. In this paper, a multi-objective genetic algorithm is proposed for floorplanning that si...

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Bibliographic Details
Main Authors: Fernando, P., Katkoori, S.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Computer science
Design engineering
Genetic algorithms
Genetic engineering
Minimization methods
Reliability engineering
Simulated annealing
Sorting
Very large scale integration
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Summary:VLSI floor-planning in the gigascale era must deal with multiple objectives including wiring congestion, performance and reliability. Genetic algorithms lend themselves naturally to multi-objective optimization. In this paper, a multi-objective genetic algorithm is proposed for floorplanning that simultaneously minimizes area and total wirelength. The proposed genetic floorplanner is the first to use non-domination concepts to rank solutions. Two novel crossover operators are presented that build floorplans using good sub-floorplans. The efficiency of the proposed approach is illustrated by the 18% wirelength savings and 4.6% area savings obtained for the GSRC benchmarks and 26% wirelength savings for the MCNC benchmarks for a marginal 1.3% increase in area when compared to previous floorplanners that perform simultaneous area and wirelength minimization.
ISSN:1063-9667
2380-6923
DOI:10.1109/VLSI.2008.97