New Ultra Thin Chip Scale Package (CSP) based on Thermo-Sonic Flip-Chip Interconnection

This paper introduces a new chip scale package (CSP) platform, and its assembly process flow in detail. The concept uses the ultra-sonic / thermo-sonic flip-chip bonding of die onto re-distribution layer (RDL) pre-plated metal substrate. Package is then encapsulated with mold compound for structural...

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Bibliographic Details
Main Authors: Seung-Yong Choi, Ching-Shian Ti, Min-Hyo Park, Seng-Teong Chang
Format: Conference Proceeding
Language:English
Subjects:
Assembly
Bonding
Chemical compounds
Chemical processes
Chip scale packaging
Etching
Flip chip
Resists
Robustness
Wire
Online Access:Request full text
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Summary:This paper introduces a new chip scale package (CSP) platform, and its assembly process flow in detail. The concept uses the ultra-sonic / thermo-sonic flip-chip bonding of die onto re-distribution layer (RDL) pre-plated metal substrate. Package is then encapsulated with mold compound for structural robustness before the removal of the metal substrate through chemical etching process. The exposed areas is passivated with patterned solder resist layer covering the RDL at the same time creating opening for second level interconnection to the board. The flip chip interconnection enhances electrical and thermal performance compared to wire bonded package, and also provides ultra thin profile as well as small footprint area. The package passes all reliability tests without any failures including moisture sensitivity level 1 (MSL 1), Autoclave and TMCL for component level, and board level drop and TMCL.
DOI:10.1109/EPTC.2007.4469805