Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits

This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many inst...

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Main Authors: Feinstein, D.Y., Thornton, M.A., Miller, D.M.
Format: Conference Proceeding
Language:English
Subjects:
Automatic logic units
Circuit simulation
Circuit synthesis
Circuit testing
Computer science
Logic circuits
Logic design
Logic gates
Logic testing
Redundancy
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Thornton, M.A.
Miller, D.M.
description This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.
doi_str_mv 10.1109/DATE.2008.4484932
format conference_proceeding
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1558-1101
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source IEEE Xplore All Conference Series
subjects Automatic logic units
Circuit simulation
Circuit synthesis
Circuit testing
Computer science
Logic circuits
Logic design
Logic gates
Logic testing
Redundancy
title Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits
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