Low-power bufferless resonant clock distribution networks

The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In a...

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Bibliographic Details
Main Authors: Mesgarzadeh, B., Hansson, M., Alvandpour, A.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Feedback
Frequency
Jitter
Measurement standards
Parasitic capacitance
Q factor
Resonance
Semiconductor device measurement
Testing
Online Access:Request full text
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Description
Summary:The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2007.4488725