A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error de...

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Main Authors: Bae, Seung-Jun, Sohn, Young-Soo, Park, Kwang-Il, Kim, Kyoung-Ho, Chung, Dae-Hyun, Kim, Jin-Gook, Kim, Si-Hong, Park, Min-Sang, Lee, Jae-Hyung, Bang, Sam-Young, Lee, Ho-Kyung, Park, In-Soo, Kim, Jae-Sung, Kim, Dae-Hyun, Kim, Hye-Ran, Shin, Yong-Jae, Park, Cheol-Goo, Moon, Gil-Shin, Yeom, Ki-Woong, Kim, Kang-Young, Lee, Jae-Young, Yang, Hyang-Ja, Jang, Seong-Jin, Choi, Joo Sun, Jun, Young-Hyun, Kim, Kinam
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Clocks
Feedback
Filters
Graphics
Intersymbol interference
Phase locked loops
Random access memory
Resistors
Switches
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Summary:Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding. This work tackles challenges in GDDR5 such as clock jitter and signal integrity.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2008.4523165