90nm Games Processor Wafer to Module Power Yield Optimization

When fabricating a high volume games processor (CPU) for the consumer market, due to the cost of the module package, it is important to optimize the functional yield loss between the wafer die and the finished module package. For a performance CPU in a mature 90 nm technology the primary yield drive...

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Bibliographic Details
Main Authors: Mallette, R., Rawlins, B.
Format: Conference Proceeding
Language:English
Subjects:
CMOS Device Gate Leakage
CMOS Device Process Variability
CMOS process
CMOS technology
Cost function
Current measurement
Gate leakage
Iddq Screening
Microelectronics
Packaging
Performance loss
Power measurement
Semiconductor device testing
Wafer to Module Test Yield Optimization
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Description
Summary:When fabricating a high volume games processor (CPU) for the consumer market, due to the cost of the module package, it is important to optimize the functional yield loss between the wafer die and the finished module package. For a performance CPU in a mature 90 nm technology the primary yield drivers can be power and performance. A functional power Iddq screen test method is presented here that decreases yield loss across functional test sectors by minimizing the impact of process variation for device gate leakage.
ISSN:1078-8743
2376-6697
DOI:10.1109/ASMC.2008.4529050