Realization of Silicon-Germanium-Tin (SiGeSn) Source/Drain Stressors by Sn implant and Solid Phase Epitaxy for strain engineering in SiGe channel P-MOSFETs

• Main Authors: Wang, G.H., Eng-Huat Toh, Taw Kuei Chan, Osipowicz, T., Yong-Lim Foo, Chih Hang Tung, Guo-Qiang Lo, Samudra, G., Yee-Chia Yeo
• Format: Conference Proceeding
• Language: English
• Subjects: Capacitive sensors; Costs; Epitaxial growth; Etching; Germanium silicon alloys; Implants; MOSFET circuits; Silicon germanium; Solids; Tin
• ISSN: 1524-766X; 2690-8174
• DOI: 10.1109/VTSA.2008.4530830

We report the first demonstration of silicon-germanium-tin (SiGeSn) source and drain (S/D) stressors formed by Sn implant and solid-phase epitaxy (SPE). SPE was developed to achieve high levels of Sn substitutionality in SiGe S/D, to induce compressive strain in the channel. No recess etch or epi deposition steps were required, leading to minimal incremental process cost. SiGeSn S/D can be easily integrated in a standard CMOS process. Sub-50 nm p-FETs were fabricated. With a substitutional Sn concentration of 6.6% in SiGe S/D, having an equivalent lattice constant to that of Si 0.4 Ge 0.6 , enhancement of I Dsat and hole mobility (μ hole ) are 48% and 88% respectively, over p-FETs without Sn implant. With the demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FET enhancement.