Cluster Ion Implantation for beyond 45nm node novel device applications

• Main Authors: Tanjyo, M., Nagayama, T., Hamamoto, N., Umisedo, S., Koga, Y., Maehara, N., Matsumoto, T., Nagai, N., Ootsuka, F., Katakami, A., Shirai, K., Watanabe, T., Nakata, H., Kitajima, M., Aoyama, T., Eimori, T., Nara, Y., Ohji, Y., Saker, K., Krull, W., Jacobson, D., Horsky, T.
• Format: Conference Proceeding
• Language: English
• Subjects: Annealing; Boron; Electric variables; High K dielectric materials; High-K gate dielectrics; Ion implantation; Lamps; MOSFET circuits; Power engineering and energy; Stress
• DOI: 10.1109/IWJT.2008.4540017

This paper describes the applications of cluster ion implantation for beyond 45 nm node novel devices. A) Metal/high-k MOSFET: a flash lamp annealing (FLA) has advantage of dopant diffusion-less characteristics, but it requires suitable angle control for optimum gate overlap length. Cluster boron implantation with tilted SDE implantation for p-FETs has superiority over monomer boron implantation with Ge PAI (pre-amorphous implantation) in terms of VTH roll-off s and ion-ioff s if FLA is used as activation anneal. Full-metal-gate HfSiON transistors whose gate length is less than 50 nm are fabricated with superior electrical characteristics. B) n-MOS stress engineering: Si:C formation with high carbon substitution has been obtained using cluster carbon implantation and msec annealing which leads to higher stress in the channel region. C) Fin-FET: high tilt angle with low energy boron cluster ion implantation is found to improve the retained dose compared to monomer boron. It is suitable for Fin-FET implantation applications.