Full-chip to device level 3D thermal analysis of RF integrated circuits

• Main Authors: Turowski, M., Dooley, S., Wilkerson, P., Raman, A., Casto, M.
• Format: Conference Proceeding
• Language: English
• Subjects: BiCMOS integrated circuits; design; dissipated power; Germanium silicon alloys; gradients; heat; hot spots; Integrated circuit layout; Integrated circuit modeling; layout; modeling; multi-scale; Process design; Radio frequency; Radiofrequency integrated circuits; SiGe HBT; Silicon germanium; simulation; temperature; Temperature distribution; thermal; Thermal conductivity; three-dimensional
• ISSN: 1087-9870; 2577-0799
• DOI: 10.1109/ITHERM.2008.4544286

A multi-scale modeling approach is proposed and employed to investigate thermal issues and to enable "thermally aware" design of radio-frequency (RF) integrated circuits (ICs). Thermal analysis from full-chip scale down to the single transistor level was made possible with the development of this approach using the finite volume three-dimensional (3D) numerical technique. We have developed new tools that import GDSII layout of entire IC and, for the purpose of generating full-chip 3D thermal model, automatically eliminate the minuscule layout elements that do not affect thermal results. We present here our approach and examples of using equivalent thermal conductivity blocks in place of "forest of vias" typical in modern ICs. Our method and tools are demonstrated on a couple of RF ICs based on a high performance SiGe BiCMOS technology. The tool provides a 3D temperature map that can show thermal gradients across a chip, as well as local temperature distribution (hot spots) down to single transistor level. This allows introducing temperature back into design process. The multi-scale modeling is verified with infrared temperature measurements.