3D fracture mechanics analysis of underfill delamination for flip chip packages

In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, copper heat spreader and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamina...

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Bibliographic Details
Main Authors: Zhen Zhang, Zhai, C.J., Master, R.N.
Format: Conference Proceeding
Language:English
Subjects:
Assembly
Copper
Delamination
FEA
Flip chip
Packaging
Silicon
Testing
Thermal expansion
Thermal force
Thermal stresses
underfill
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Summary:In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, copper heat spreader and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamination on various interfaces involving a range of length scales from hundreds of nanometers to millimeters. Among these failures underfill delamination is a dominant failure mode. In this paper, a full parametric 3D model of flip chip package with heat spreader is developed with the capability of explicit modeling of 3D cracks. The crack driving force is computed as the functions of underfill properties including coefficient of thermal expansion and Young's modulus, as well as underfill fillet dimensions. The impact of different shapes of crack front is also investigated. The results show that underfill properties need to be optimized to minimize the occurrence of underfill delamination at the die corner. The results also show that there exists an optimal range of underfill fillet height to balance the manufacturability and reliability.
ISSN:1087-9870
2577-0799
DOI:10.1109/ITHERM.2008.4544343