Simulation-Based Approach for Evaluating On-Chip Interconnect Architectures

• Main Authors: Suboh, S., Bakhouya, M., Lopez-Buedo, S., El-Ghazawi, T.
• Format: Conference Proceeding
• Language: English
• Subjects: Energy consumption; Energy efficiency; Frequency; Measurement; Network-on-a-chip; Routing; Scalability; System-on-a-chip; Topology; Traffic control
• DOI: 10.1109/SPL.2008.4547735

On-chip interconnect (OCI) plays a prime role in the entire system-on-chip performance, energy consumption, and area requirements. OCI has become a successful research field given the dramatic increase in the number of processors and other functional units (IPs) that need to be integrated on a single chip. Current systems-on-chip (SoCs) use bus- based systems which become a bottleneck because of scalability, energy efficiency and frequency limitations. New sophisticated interconnects were recently proposed as a re search direction in SoC design, including distinct topologies and specific routing and switching techniques. This paper analyzes and compares five common NoC configurations, 2D mesh, ring, spidergon, fat-tree(FT) and butterfly fat-tree (BFT). These configurations are simulated for different traffic scenarios that imitate certain application domains, and comparison results for different performance metrics are presented.