Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing

Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with...

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Bibliographic Details
Main Authors: Sugizaki, Y., Nakao, M., Higuchi, K., Miyagi, T., Obata, S., Inoue, M., Endo, M., Shimooka, Y., Kojima, A., Mori, I., Shibata, H.
Format: Conference Proceeding
Language:English
Subjects:
Chip scale packaging
Gold
Joining processes
Micromechanical devices
Stacking
Surfaces
Transistors
Wafer bonding
Wafer scale integration
Wires
Online Access:Request full text
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Summary:Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.
ISSN:0569-5503
2377-5726
DOI:10.1109/ECTC.2008.4550068