Loading…
Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing
Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with...
Saved in:
| Main Authors: | , , , , , , , , , , |
|---|---|
| Format: | Conference Proceeding |
| Language: | English |
| Subjects: | |
| Online Access: | Request full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| cited_by | |
|---|---|
| cites | |
| container_end_page | 816 |
| container_issue | |
| container_start_page | 811 |
| container_title | |
| container_volume | |
| creator | Sugizaki, Y. Nakao, M. Higuchi, K. Miyagi, T. Obata, S. Inoue, M. Endo, M. Shimooka, Y. Kojima, A. Mori, I. Shibata, H. |
| description | Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device. |
| doi_str_mv | 10.1109/ECTC.2008.4550068 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4550068</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4550068</ieee_id><sourcerecordid>4550068</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-72804bf9e6d49eff7f15dcc7482ff09eabfe2fb48b8c5555db0288027769118d3</originalsourceid><addsrcrecordid>eNpVkMtOwzAURM1LIir5AMTGP5D0-hXbS2SlpVILSC3rKomvqSGlKImo-HuC6IazmZFGM4sh5JZBzhjYaek2LucAJpdKARTmjKRWGya5lJwLZs9JwoXWmdK8uPiXAb8kCajCZmNTXJO0799gRCpRCJ2Q2ePhC1t6rAJ2WYu_3q2faTh0tB-q5h09XZWrNZ3ShaM-Yk-PcdjRHXZ7HGJDe6za-PF6Q65C1faYnnRCXmblxj1ky6f5wt0vs8i0GjLNDcg6WCy8tBiCDkz5ptHS8BDAYlUH5KGWpjaNGvE1cGOAa11YxowXE3L3txsRcfvZxX3VfW9Pr4gfqoFPMQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Sugizaki, Y. ; Nakao, M. ; Higuchi, K. ; Miyagi, T. ; Obata, S. ; Inoue, M. ; Endo, M. ; Shimooka, Y. ; Kojima, A. ; Mori, I. ; Shibata, H.</creator><creatorcontrib>Sugizaki, Y. ; Nakao, M. ; Higuchi, K. ; Miyagi, T. ; Obata, S. ; Inoue, M. ; Endo, M. ; Shimooka, Y. ; Kojima, A. ; Mori, I. ; Shibata, H.</creatorcontrib><description>Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.</description><identifier>ISSN: 0569-5503</identifier><identifier>ISBN: 9781424422302</identifier><identifier>ISBN: 1424422302</identifier><identifier>EISSN: 2377-5726</identifier><identifier>EISBN: 9781424422319</identifier><identifier>EISBN: 1424422310</identifier><identifier>DOI: 10.1109/ECTC.2008.4550068</identifier><language>eng</language><publisher>IEEE</publisher><subject>Chip scale packaging ; Gold ; Joining processes ; Micromechanical devices ; Stacking ; Surfaces ; Transistors ; Wafer bonding ; Wafer scale integration ; Wires</subject><ispartof>2008 58th Electronic Components and Technology Conference, 2008, p.811-816</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4550068$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54554,54919,54931</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4550068$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sugizaki, Y.</creatorcontrib><creatorcontrib>Nakao, M.</creatorcontrib><creatorcontrib>Higuchi, K.</creatorcontrib><creatorcontrib>Miyagi, T.</creatorcontrib><creatorcontrib>Obata, S.</creatorcontrib><creatorcontrib>Inoue, M.</creatorcontrib><creatorcontrib>Endo, M.</creatorcontrib><creatorcontrib>Shimooka, Y.</creatorcontrib><creatorcontrib>Kojima, A.</creatorcontrib><creatorcontrib>Mori, I.</creatorcontrib><creatorcontrib>Shibata, H.</creatorcontrib><title>Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing</title><title>2008 58th Electronic Components and Technology Conference</title><addtitle>ECTC</addtitle><description>Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.</description><subject>Chip scale packaging</subject><subject>Gold</subject><subject>Joining processes</subject><subject>Micromechanical devices</subject><subject>Stacking</subject><subject>Surfaces</subject><subject>Transistors</subject><subject>Wafer bonding</subject><subject>Wafer scale integration</subject><subject>Wires</subject><issn>0569-5503</issn><issn>2377-5726</issn><isbn>9781424422302</isbn><isbn>1424422302</isbn><isbn>9781424422319</isbn><isbn>1424422310</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpVkMtOwzAURM1LIir5AMTGP5D0-hXbS2SlpVILSC3rKomvqSGlKImo-HuC6IazmZFGM4sh5JZBzhjYaek2LucAJpdKARTmjKRWGya5lJwLZs9JwoXWmdK8uPiXAb8kCajCZmNTXJO0799gRCpRCJ2Q2ePhC1t6rAJ2WYu_3q2faTh0tB-q5h09XZWrNZ3ShaM-Yk-PcdjRHXZ7HGJDe6za-PF6Q65C1faYnnRCXmblxj1ky6f5wt0vs8i0GjLNDcg6WCy8tBiCDkz5ptHS8BDAYlUH5KGWpjaNGvE1cGOAa11YxowXE3L3txsRcfvZxX3VfW9Pr4gfqoFPMQ</recordid><startdate>200805</startdate><enddate>200805</enddate><creator>Sugizaki, Y.</creator><creator>Nakao, M.</creator><creator>Higuchi, K.</creator><creator>Miyagi, T.</creator><creator>Obata, S.</creator><creator>Inoue, M.</creator><creator>Endo, M.</creator><creator>Shimooka, Y.</creator><creator>Kojima, A.</creator><creator>Mori, I.</creator><creator>Shibata, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200805</creationdate><title>Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing</title><author>Sugizaki, Y. ; Nakao, M. ; Higuchi, K. ; Miyagi, T. ; Obata, S. ; Inoue, M. ; Endo, M. ; Shimooka, Y. ; Kojima, A. ; Mori, I. ; Shibata, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-72804bf9e6d49eff7f15dcc7482ff09eabfe2fb48b8c5555db0288027769118d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Chip scale packaging</topic><topic>Gold</topic><topic>Joining processes</topic><topic>Micromechanical devices</topic><topic>Stacking</topic><topic>Surfaces</topic><topic>Transistors</topic><topic>Wafer bonding</topic><topic>Wafer scale integration</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Sugizaki, Y.</creatorcontrib><creatorcontrib>Nakao, M.</creatorcontrib><creatorcontrib>Higuchi, K.</creatorcontrib><creatorcontrib>Miyagi, T.</creatorcontrib><creatorcontrib>Obata, S.</creatorcontrib><creatorcontrib>Inoue, M.</creatorcontrib><creatorcontrib>Endo, M.</creatorcontrib><creatorcontrib>Shimooka, Y.</creatorcontrib><creatorcontrib>Kojima, A.</creatorcontrib><creatorcontrib>Mori, I.</creatorcontrib><creatorcontrib>Shibata, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sugizaki, Y.</au><au>Nakao, M.</au><au>Higuchi, K.</au><au>Miyagi, T.</au><au>Obata, S.</au><au>Inoue, M.</au><au>Endo, M.</au><au>Shimooka, Y.</au><au>Kojima, A.</au><au>Mori, I.</au><au>Shibata, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing</atitle><btitle>2008 58th Electronic Components and Technology Conference</btitle><stitle>ECTC</stitle><date>2008-05</date><risdate>2008</risdate><spage>811</spage><epage>816</epage><pages>811-816</pages><issn>0569-5503</issn><eissn>2377-5726</eissn><isbn>9781424422302</isbn><isbn>1424422302</isbn><eisbn>9781424422319</eisbn><eisbn>1424422310</eisbn><abstract>Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.</abstract><pub>IEEE</pub><doi>10.1109/ECTC.2008.4550068</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0569-5503 |
| ispartof | 2008 58th Electronic Components and Technology Conference, 2008, p.811-816 |
| issn | 0569-5503 2377-5726 |
| language | eng |
| recordid | cdi_ieee_primary_4550068 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Chip scale packaging Gold Joining processes Micromechanical devices Stacking Surfaces Transistors Wafer bonding Wafer scale integration Wires |
| title | Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T16%3A08%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Novel%20wafer-level%20CSP%20for%20stacked%20MEMS%20/%20IC%20dies%20with%20hermetic%20sealing&rft.btitle=2008%2058th%20Electronic%20Components%20and%20Technology%20Conference&rft.au=Sugizaki,%20Y.&rft.date=2008-05&rft.spage=811&rft.epage=816&rft.pages=811-816&rft.issn=0569-5503&rft.eissn=2377-5726&rft.isbn=9781424422302&rft.isbn_list=1424422302&rft_id=info:doi/10.1109/ECTC.2008.4550068&rft.eisbn=9781424422319&rft.eisbn_list=1424422310&rft_dat=%3Cieee_6IE%3E4550068%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-72804bf9e6d49eff7f15dcc7482ff09eabfe2fb48b8c5555db0288027769118d3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4550068&rfr_iscdi=true |