Robust hermetic wafer level thin-film encapsulation technology for stacked MEMS / IC package

• Main Authors: Shimooka, Y., Inoue, M., Endo, M., Obata, S., Kojima, A., Miyagi, T., Sugizaki, Y., Mori, I., Shibata, H.
• Format: Conference Proceeding
• Language: English
• Subjects: Chemical technology; Encapsulation; Integrated circuit packaging; Micromechanical devices; Robustness; Semiconductor thin films; Sputtering; Thin film circuits; Transistors; Wafer scale integration
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2008.4550071

This paper reports a thin-film encapsulation technology for wafer level micro-electro-mechanical systems (MEMS) package, using poly-benzo-oxazole (PBO) sacrificial material and plasma enhanced chemical vapor deposited silicon oxide (PECVD SiO) cap layer. This technique, which is applicable for MEMS technologies, saves die size and enables conventional package processes such as dicing, picking, mounting and bonding. Besides the fabrication processes of the thin-film encapsulation, this paper also presents the results of finite element models (FEMs) for the deflection and the mechanical stress of the thin-film caps. Moreover, in order to mount a MEMS chip with the thin- film capsulations and another integrated circuit (IC) chip that controls a MEMS chip in the same package, we have also developed an epoxy reinforcement technique for protecting the thin-film encapsulations and a topography wafer thinning technique for the MEMS chip. And then the system in package (SiP) for the MEMS and IC chips is fabricated successfully based on the mechanical analysis of the SiP process.