Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis

On chip signal crosstalk is a function of switching activity pattern, coupling parasitics, and signal timing. We propose a simulated annealing (SA) based high-level synthesis algorithm for crosstalk activity minimization for a given data environment. We target bus-based architectures as the bus-line...

Full description

Saved in:
Bibliographic Details
Main Authors: Sankaran, H., Katkoori, S.
Format: Conference Proceeding
Language:English
Subjects:
allocation
binding
Bus based designs
Capacitance
Crosstalk
Delay
Design optimization
Digital signal processing
Encoding
High level synthesis
HLS
Re-ordering
scheduling
Signal synthesis
Simulated annealing
Wires
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:On chip signal crosstalk is a function of switching activity pattern, coupling parasitics, and signal timing. We propose a simulated annealing (SA) based high-level synthesis algorithm for crosstalk activity minimization for a given data environment. We target bus-based architectures as the bus-lines have well-defined neighborhood (aggressors). Our objective is to minimize worst-case crosstalk patterns by exploring synthesis solutions with correlations that do not result in such worst-case patterns. Besides synthesis moves, we also incorporate bus re-ordering and data transfer invert encoding. Experimental results for design under resource as well as latency constraints are promising. For a set of three DSP benchmarks we reduce up to 75% of buses that require no shielding lines.
ISSN:2159-3469
2159-3477
DOI:10.1109/ISVLSI.2008.95