Pentacene - SiO2 interface: Role of the environment prior to pentacene deposition and its impact on TFT DC characteristics

In this paper we report on the effect of the environment on the SiO 2 /pentacene interface. Two batches of bottom-contact pentacene thin-film transistors have been fabricated with a 100 nm thick SiO 2 as dielectric. Considerable shifts of the threshold voltages have been observed for the TFTs whose...

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Bibliographic Details
Main Authors: Cvetkovic, N.V., Tsamados, D., Sidler, K., Brugger, J., Ionescu, A.M.
Format: Conference Proceeding
Language:English
Subjects:
Dielectrics
Gold
Microelectronics
Organic thin film transistors
Pentacene
Plasma devices
Plasma temperature
Surface treatment
Thin film transistors
Threshold voltage
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Summary:In this paper we report on the effect of the environment on the SiO 2 /pentacene interface. Two batches of bottom-contact pentacene thin-film transistors have been fabricated with a 100 nm thick SiO 2 as dielectric. Considerable shifts of the threshold voltages have been observed for the TFTs whose dielectric surface has been exposed to air for long periods of storage before depositing the pentacene layer. Based on reports from other research groups in the field, we consider that long exposure of the SiO 2 to air may have the same effect on the SiO 2 -pentace interface as short but more aggressive oxygen plasma treatment.
DOI:10.1109/ICMEL.2008.4559282