An area efficient high turn ratio monolithic transformer for silicon RFIC

A novel way of manufacturing an on-chip transformer that produces high inductance ratio (L Sec /L Pri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (primary coil), having large effective width, and a densely routed...

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Bibliographic Details
Main Authors: Chee Chong Lim, Kiat Seng Yeo, Kok Wai Chew, Suh Fei Lim, Chirn Chye Boon, Qiu-ping, Manh Anh Do, Lap Chan
Format: Conference Proceeding
Language:English
Subjects:
Coils
Conductors
Coupling coefficient
Couplings
High Turn Ratio transformer
Inductance
Inductance Ratio
Inductors
Interleaved transformer
Manufacturing
Radio frequency
Radiofrequency integrated circuits
RFCMOS
Routing
Silicon
SoC
Stacked transformer
Vertical Deck
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Description
Summary:A novel way of manufacturing an on-chip transformer that produces high inductance ratio (L Sec /L Pri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (primary coil), having large effective width, and a densely routed conductor B (secondary coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is realizable on silicon. The coil having the dense routing can also be doubled up as a monolithic RF choke on silicon. In this work, area efficiency is compared between various type of existing transformer structures (i.e. interleaved and stacked transformer), based on unit inductance. The method presented is fully compatible to all the foundry standard CMOS processes.
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2008.4561410