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An area efficient high turn ratio monolithic transformer for silicon RFIC
A novel way of manufacturing an on-chip transformer that produces high inductance ratio (L Sec /L Pri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (primary coil), having large effective width, and a densely routed...
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| creator | Chee Chong Lim Kiat Seng Yeo Kok Wai Chew Suh Fei Lim Chirn Chye Boon Qiu-ping Manh Anh Do Lap Chan |
| description | A novel way of manufacturing an on-chip transformer that produces high inductance ratio (L Sec /L Pri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (primary coil), having large effective width, and a densely routed conductor B (secondary coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is realizable on silicon. The coil having the dense routing can also be doubled up as a monolithic RF choke on silicon. In this work, area efficiency is compared between various type of existing transformer structures (i.e. interleaved and stacked transformer), based on unit inductance. The method presented is fully compatible to all the foundry standard CMOS processes. |
| doi_str_mv | 10.1109/RFIC.2008.4561410 |
| format | conference_proceeding |
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The method presented is fully compatible to all the foundry standard CMOS processes.</description><subject>Coils</subject><subject>Conductors</subject><subject>Coupling coefficient</subject><subject>Couplings</subject><subject>High Turn Ratio transformer</subject><subject>Inductance</subject><subject>Inductance Ratio</subject><subject>Inductors</subject><subject>Interleaved transformer</subject><subject>Manufacturing</subject><subject>Radio frequency</subject><subject>Radiofrequency integrated circuits</subject><subject>RFCMOS</subject><subject>Routing</subject><subject>Silicon</subject><subject>SoC</subject><subject>Stacked transformer</subject><subject>Vertical Deck</subject><issn>1529-2517</issn><issn>2375-0995</issn><isbn>9781424418084</isbn><isbn>1424418089</isbn><isbn>1424418097</isbn><isbn>9781424418091</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1kMtKAzEYheMNrHUeQNzkBWbMn_u_LMVqoSCIrksyydjIXCQzLnx7R1rP5lscOJxzCLkDVgEwfHjdbNcVZ8xWUmmQwM7IDUguJViG5pwsuDCqZIjqghRo7L9n5SVZgOJYcgXmmhTj-MlmSSU46AXZrnrqcnQ0Nk2qU-wnekgfBzp9555mN6WBdkM_tGk6pJpO2fVjM-QuZjqDjqlN9dDTv3a35Kpx7RiLE5fkffP4tn4udy9P2_VqVyYQgpVBzivQ2oDeIDq0XgWmNLeBq-gg-LqphQ5R1WiN06jBCyV9NBAM816LJbk_5qYY4_4rp87ln_3pFfEL2HRQvA</recordid><startdate>200806</startdate><enddate>200806</enddate><creator>Chee Chong Lim</creator><creator>Kiat Seng Yeo</creator><creator>Kok Wai Chew</creator><creator>Suh Fei Lim</creator><creator>Chirn Chye Boon</creator><creator>Qiu-ping</creator><creator>Manh Anh Do</creator><creator>Lap Chan</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200806</creationdate><title>An area efficient high turn ratio monolithic transformer for silicon RFIC</title><author>Chee Chong Lim ; Kiat Seng Yeo ; Kok Wai Chew ; Suh Fei Lim ; Chirn Chye Boon ; Qiu-ping ; Manh Anh Do ; Lap Chan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1330-d4200988d9b799a98b5d05628d25ea1dbcfc36de5c987a6961b354be71d70bb63</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Coils</topic><topic>Conductors</topic><topic>Coupling coefficient</topic><topic>Couplings</topic><topic>High Turn Ratio transformer</topic><topic>Inductance</topic><topic>Inductance Ratio</topic><topic>Inductors</topic><topic>Interleaved transformer</topic><topic>Manufacturing</topic><topic>Radio frequency</topic><topic>Radiofrequency integrated circuits</topic><topic>RFCMOS</topic><topic>Routing</topic><topic>Silicon</topic><topic>SoC</topic><topic>Stacked transformer</topic><topic>Vertical Deck</topic><toplevel>online_resources</toplevel><creatorcontrib>Chee Chong Lim</creatorcontrib><creatorcontrib>Kiat Seng Yeo</creatorcontrib><creatorcontrib>Kok Wai Chew</creatorcontrib><creatorcontrib>Suh Fei Lim</creatorcontrib><creatorcontrib>Chirn Chye Boon</creatorcontrib><creatorcontrib>Qiu-ping</creatorcontrib><creatorcontrib>Manh Anh Do</creatorcontrib><creatorcontrib>Lap Chan</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chee Chong Lim</au><au>Kiat Seng Yeo</au><au>Kok Wai Chew</au><au>Suh Fei Lim</au><au>Chirn Chye Boon</au><au>Qiu-ping</au><au>Manh Anh Do</au><au>Lap Chan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An area efficient high turn ratio monolithic transformer for silicon RFIC</atitle><btitle>2008 IEEE Radio Frequency Integrated Circuits Symposium</btitle><stitle>RFIC</stitle><date>2008-06</date><risdate>2008</risdate><spage>167</spage><epage>170</epage><pages>167-170</pages><issn>1529-2517</issn><eissn>2375-0995</eissn><isbn>9781424418084</isbn><isbn>1424418089</isbn><eisbn>1424418097</eisbn><eisbn>9781424418091</eisbn><abstract>A novel way of manufacturing an on-chip transformer that produces high inductance ratio (L Sec /L Pri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (primary coil), having large effective width, and a densely routed conductor B (secondary coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is realizable on silicon. The coil having the dense routing can also be doubled up as a monolithic RF choke on silicon. In this work, area efficiency is compared between various type of existing transformer structures (i.e. interleaved and stacked transformer), based on unit inductance. The method presented is fully compatible to all the foundry standard CMOS processes.</abstract><pub>IEEE</pub><doi>10.1109/RFIC.2008.4561410</doi><tpages>4</tpages><oa>free_for_read</oa></addata></record> |
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| identifier | ISSN: 1529-2517 |
| ispartof | 2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008, p.167-170 |
| issn | 1529-2517 2375-0995 |
| language | eng |
| recordid | cdi_ieee_primary_4561410 |
| source | IEEE Xplore All Conference Series |
| subjects | Coils Conductors Coupling coefficient Couplings High Turn Ratio transformer Inductance Inductance Ratio Inductors Interleaved transformer Manufacturing Radio frequency Radiofrequency integrated circuits RFCMOS Routing Silicon SoC Stacked transformer Vertical Deck |
| title | An area efficient high turn ratio monolithic transformer for silicon RFIC |
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