A model-driven validation & verification environment for embedded systems

This paper presents a validation and verification tool component, based on the abstract state machine formal method, that we are developing to support high level formal analysis of embedded system model-driven design. This component is integrated into a model-driven environment for HW/SW co-design t...

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Bibliographic Details
Main Authors: Gargantini, A., Riccobene, E., Scandurra, P.
Format: Conference Proceeding
Language:English
Subjects:
Application software
Computer architecture
Diffusion tensor imaging
Embedded system
Hardware
Industrial control
Job shop scheduling
Standardization
Timing
Unified modeling language
Online Access:Request full text
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Description
Summary:This paper presents a validation and verification tool component, based on the abstract state machine formal method, that we are developing to support high level formal analysis of embedded system model-driven design. This component is integrated into a model-driven environment for HW/SW co-design that provides a graphical high-level representation of HW and SW components by means of UML profiles for SystemC/multi-thread C, and allows C/C++/SystemC code generation/back-annotation from/to graphical UML models.
ISSN:2150-3109
2150-3117
DOI:10.1109/SIES.2008.4577708