Design and Analysis of Direct Digital Frequency Synthesizer

• Main Authors: Khilar, S., Kiran Parmar, Saumi, S., Dasgupta, K.S.
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; Converters; Frequency synthesizers; MATLAB; Noise; quantization; Read only memory; sine ROM; spurius; synthesizer; Table lookup
• ISSN: 2157-0477; 2157-0485
• DOI: 10.1109/ICETET.2008.60

This paper consists of design and analysis of direct digital frequency synthesizer (DDFS). Its key elements are: phase accumulator, a phase to amplitude converter (sine ROM) also called look-up table (LUT), a digital to analog converter (DAC) and a filter. The phase values are generated using modulo 2N overflowing property of a N-bit phase accumulator. Higher compression in ROM is achieved, by taking an advantage of the quadrant symmetry of sine function in 0 to pi/2 interval. The distinguishing feature of this design is the implementation of 48 bits frequency control word (FCW) in accumulator, which results nearly same spurious level as that obtained in 32 bits FCW. An actual DDFS designing is performed which provides simulated ~70 dBc spectral purity, 35.5nHz frequency resolution and 12 bits output digital data at a maximum simulated clock frequency of 10 MHz. This paper also includes analysis of phase truncation effect and relevant techniques to overcome this truncation like phase dithering. This DDFS generates frequency resolution in the sub hertz range which make it ideal components in software defined radios, radar systems, navigational satellites and modern spread spectrum wireless communication systems.