A teraBit/s-throughput, SerDes-based interface for a third-generation 16 core 32 thread chip-multithreading SPARC processor

Third-generation 16 core 32 thread chip-multithreading SPARC processor interface has 1.1 Tbps I/O throughput with 112 Tx/176 Rx SerDes channels in 46 mm 2 . Individual links run at BER of 1E-12 on FR4 PCBs at 4.08-0.5 Gbps full-half rate, and 18 mW/ch/Gbps at 2.67 Gbps. Each link has linear equaliza...

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Bibliographic Details
Main Authors: Nasrullah, J., Amin, A., Ahmad, W., Zuxu Qin, Mushtaq, Z., Javed, O., Joon Yoon, Chua, L., Dawei Huang, Baoqing Huang, Vichare, M., Ho, K., Rashid, M.
Format: Conference Proceeding
Language:English
Subjects:
Adaptive systems
Clocks
Equalizers
Phase locked loops
Receivers
Throughput
Transceivers
Online Access:Request full text
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Summary:Third-generation 16 core 32 thread chip-multithreading SPARC processor interface has 1.1 Tbps I/O throughput with 112 Tx/176 Rx SerDes channels in 46 mm 2 . Individual links run at BER of 1E-12 on FR4 PCBs at 4.08-0.5 Gbps full-half rate, and 18 mW/ch/Gbps at 2.67 Gbps. Each link has linear equalization, 15 deemphasis and 8 output-swing control settings, and latency of 8UI in Rx and 14-16UI in Tx.
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2008.4586006