A novel pseudo tri-gate vertical MOSFET with source/drain tie

This paper investigates the device behaviours of a pseudo tri-gate ultra-thin-channel vertical MOSFET with source/drain tie. For comparison two transistors are designed. According to the 2D simulation, our proposed structure can effectively enhance the drain current and the thermal stability, mainly...

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Bibliographic Details
Main Authors: Jyi-Tsong Lin, Ying-Chieh Tsai, Yi-Chuen Eng, Shiang-Shi Kang, Yi-Ming Tseng, Hung-Jen Tseng, Po-Hsieh Lin
Format: Conference Proceeding
Language:English
Subjects:
Lattices
Logic gates
MOSFET circuits
Reliability
Thermal stability
Threshold voltage
Transistors
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Summary:This paper investigates the device behaviours of a pseudo tri-gate ultra-thin-channel vertical MOSFET with source/drain tie. For comparison two transistors are designed. According to the 2D simulation, our proposed structure can effectively enhance the drain current and the thermal stability, mainly due to the ultrathin channel (Tsi = 10 nm). The fabricated device have very low subthreshold swing near 60 mV/dec with channel length 40 nm to 90 nm and excellent G M of 4 mS/mum with channel length 35 nm owing to its unique features, when compared to its counterpart. Also, the respective discontinuous buried oxide under the channel and the source/drain regions can construct a natural source/drain tie to overcome short-channel effects and self-heating effects as well.
ISSN:1946-1542
1946-1550
DOI:10.1109/IPFA.2008.4588183