35-nm gate-length and ultra low-voltage (0.45 V) operation Bulk Thyristor-SRAM/DRAM (BT-RAM) cell with Triple selective Epitaxy Layers (TELs)

We have successfully developed an alternative SRAM cell using a bulk thyristor-RAM (BT-RAM), which has a 35-nm gate-length with triple selective epitaxy layers (TELs) for the anode, the n-base, and the cathode. The TEL BT-RAM reads and writes at an ultra low voltage of 0.45 V at 900 ps and reads and...

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Bibliographic Details
Main Authors: Sugizaki, T., Nakamura, M., Yanagita, M., Shinohara, M., Ikuta, T., Ohchi, T., Kugimiya, K., Kanda, S., Yagami, K., Oda, T.
Format: Conference Proceeding
Language:English
Subjects:
Anodes
Cathodes
International Electron Devices Meeting
Logic gates
Random access memory
Scalability
Thermal stability
Online Access:Request full text
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Summary:We have successfully developed an alternative SRAM cell using a bulk thyristor-RAM (BT-RAM), which has a 35-nm gate-length with triple selective epitaxy layers (TELs) for the anode, the n-base, and the cathode. The TEL BT-RAM reads and writes at an ultra low voltage of 0.45 V at 900 ps and reads and writes at a high speed of 100 ps at 0.9 V. It also has excellent scalability, a high I on /I off ratio, and good thermal stability even at 125degC. The TEL BT-RAM is therefore a promising alternative SRAM cell for the 35-nm gate length generation and beyond.
ISSN:0743-1562
DOI:10.1109/VLSIT.2008.4588617