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Register binding guided by the size of variables
An important problem is how to carry out register binding such that any register has to be bound to a set of variables such that the difference between their sizes is as small as possible. For the case of hardware implementations, satisfying this latter constraint will allow to reduce the complexity...
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creator | Chabini, N. Wolf, W. |
description | An important problem is how to carry out register binding such that any register has to be bound to a set of variables such that the difference between their sizes is as small as possible. For the case of hardware implementations, satisfying this latter constraint will allow to reduce the complexity of the clock generation tree, and saving area occupied by the registers which is very important for the case of system-on-chip and some embedded systems. When registers are already built, satisfying this latter constraint would allow reducing power consumption due to useless switching activities that will happen into any register that is bound to variables with different sizes. Assuming that the size in bits of any variable is known, we propose in this paper exact algorithms to optimally solve this problem for the case of acyclic graphs. An extended version of this problem is how to solve it while controlling the number of variables to be assigned to a same register. We also propose exact algorithms to optimally solve this latter version of the problem. Experimental results are provided. We also test the impact of the proposed approach in the case of a hardware implementation using the design analyzer tool from Synopsys Inc.. Obtained results have shown that both area and power consumption have been reduced. |
doi_str_mv | 10.1109/ICCD.2007.4601957 |
format | conference_proceeding |
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For the case of hardware implementations, satisfying this latter constraint will allow to reduce the complexity of the clock generation tree, and saving area occupied by the registers which is very important for the case of system-on-chip and some embedded systems. When registers are already built, satisfying this latter constraint would allow reducing power consumption due to useless switching activities that will happen into any register that is bound to variables with different sizes. Assuming that the size in bits of any variable is known, we propose in this paper exact algorithms to optimally solve this problem for the case of acyclic graphs. An extended version of this problem is how to solve it while controlling the number of variables to be assigned to a same register. We also propose exact algorithms to optimally solve this latter version of the problem. Experimental results are provided. We also test the impact of the proposed approach in the case of a hardware implementation using the design analyzer tool from Synopsys Inc.. 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We also test the impact of the proposed approach in the case of a hardware implementation using the design analyzer tool from Synopsys Inc.. Obtained results have shown that both area and power consumption have been reduced.</description><subject>Artificial neural networks</subject><subject>Hardware</subject><subject>Multiplexing</subject><subject>Optimization</subject><subject>Power dissipation</subject><subject>Registers</subject><subject>Switches</subject><issn>1063-6404</issn><issn>2576-6996</issn><isbn>9781424412570</isbn><isbn>1424412579</isbn><isbn>9781424412587</isbn><isbn>1424412587</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpVj81KAzEUheMfONY-gLjJC8z03vxnKWO1hYIg3ZeJuRkjtcpkFOrTW7AbV4fDd_jgMHaD0CCCny3b9r4RALZRBtBre8Km3jpUQikU2tlTVgltTW28N2f_mIVzViEYWRsF6pJdlfIGAE6irRg8U5_LSAMPeRfzruf9V44Uedjz8ZV4yT_EPxL_7obchS2Va3aRum2h6TEnbP0wX7eLevX0uGzvVnX2MNYaXfJRC4EiOhVAOkfJSoha6qCSR2dVpCDEoWn1YmXwEa0nEU2X8LCfsNs_bSaizeeQ37thvzl-l7_NQUcB</recordid><startdate>200710</startdate><enddate>200710</enddate><creator>Chabini, N.</creator><creator>Wolf, W.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200710</creationdate><title>Register binding guided by the size of variables</title><author>Chabini, N. ; Wolf, W.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-518f9d52212d84b0388ef730d535b4f91874deb225b454c73b9d179e2d6af1b03</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Artificial neural networks</topic><topic>Hardware</topic><topic>Multiplexing</topic><topic>Optimization</topic><topic>Power dissipation</topic><topic>Registers</topic><topic>Switches</topic><toplevel>online_resources</toplevel><creatorcontrib>Chabini, N.</creatorcontrib><creatorcontrib>Wolf, W.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chabini, N.</au><au>Wolf, W.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Register binding guided by the size of variables</atitle><btitle>2007 25th International Conference on Computer Design</btitle><stitle>ICCD</stitle><date>2007-10</date><risdate>2007</risdate><spage>587</spage><epage>594</epage><pages>587-594</pages><issn>1063-6404</issn><eissn>2576-6996</eissn><isbn>9781424412570</isbn><isbn>1424412579</isbn><eisbn>9781424412587</eisbn><eisbn>1424412587</eisbn><abstract>An important problem is how to carry out register binding such that any register has to be bound to a set of variables such that the difference between their sizes is as small as possible. For the case of hardware implementations, satisfying this latter constraint will allow to reduce the complexity of the clock generation tree, and saving area occupied by the registers which is very important for the case of system-on-chip and some embedded systems. When registers are already built, satisfying this latter constraint would allow reducing power consumption due to useless switching activities that will happen into any register that is bound to variables with different sizes. Assuming that the size in bits of any variable is known, we propose in this paper exact algorithms to optimally solve this problem for the case of acyclic graphs. An extended version of this problem is how to solve it while controlling the number of variables to be assigned to a same register. We also propose exact algorithms to optimally solve this latter version of the problem. Experimental results are provided. We also test the impact of the proposed approach in the case of a hardware implementation using the design analyzer tool from Synopsys Inc.. Obtained results have shown that both area and power consumption have been reduced.</abstract><pub>IEEE</pub><doi>10.1109/ICCD.2007.4601957</doi><tpages>8</tpages></addata></record> |
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identifier | ISSN: 1063-6404 |
ispartof | 2007 25th International Conference on Computer Design, 2007, p.587-594 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Artificial neural networks Hardware Multiplexing Optimization Power dissipation Registers Switches |
title | Register binding guided by the size of variables |
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