CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures

This paper describes CHiMPS, a C-based accelerator compiler for hybrid CPU-FPGA computing platforms. CHiMPSpsilas goal is to facilitate FPGA programming for high-performance computing developers. It inputs generic ANSIC code and automatically generates VHDL blocks for an FPGA. The accelerator archit...

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Bibliographic Details
Main Authors: Putnam, A., Bennett, D., Dellinger, E., Mason, J., Sundararajan, P., Eggers, S.
Format: Conference Proceeding
Language:English
Subjects:
Benchmark testing
Computer architecture
Field programmable gate arrays
Hardware
Parallel processing
Program processors
Programming
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Summary:This paper describes CHiMPS, a C-based accelerator compiler for hybrid CPU-FPGA computing platforms. CHiMPSpsilas goal is to facilitate FPGA programming for high-performance computing developers. It inputs generic ANSIC code and automatically generates VHDL blocks for an FPGA. The accelerator architecture is customized with multiple caches that are tuned to the application. Speedups of 2.8x to 36.9x (geometric mean 6.7x) are achieved on a variety of HPC benchmarks with minimal source code changes.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2008.4629927