An FPGA implementation of whitted-style ray tracing accelerator

This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3 M rays per second over realistic 3 D scenes. The future implementation with ASIC is expected to achieve real-time performance.

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Bibliographic Details
Main Authors: Woo-Chan Park, Jae-ho Nah, Jeong-Soo Park, Kyung-Ho Lee, Dong-Seok Kim, Sang-Duk Kim, Jin-Hong Park, Cheong-Ghil Kim, Yoon-Sig Kang, Sung-Bong Yang, Tack-Don Han
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Computer architecture
Field programmable gate arrays
FPGA implementation
Geometry
I.3.1 [Hardware Architecture]: Graphics processors
Image color analysis
Random access memory
Ray tracing
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Description
Summary:This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3 M rays per second over realistic 3 D scenes. The future implementation with ASIC is expected to achieve real-time performance.
DOI:10.1109/RT.2008.4634650