Scenario-based validation of embedded systems

This paper describes a scenario-based methodology for system-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existing model-driven design methodology for embedded systems based on the SystemC UML profile. It allows the designer...

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Main Authors: Gargantini, A., Riccobene, E., Scandurra, P., Carioni, A.
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Biological system modeling
Design methodology
Embedded system
Libraries
Modeling
Unified modeling language
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creator Gargantini, A.
Riccobene, E.
Scandurra, P.
Carioni, A.
description This paper describes a scenario-based methodology for system-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existing model-driven design methodology for embedded systems based on the SystemC UML profile. It allows the designer to functionally validate system components from SystemC UML designs early at high levels of abstraction and without requiring strong skills and expertise on formal methods. A validation tool integrated into an existing model-driven co-design environment to support the proposed scenario-based validation flow is also presented.
doi_str_mv 10.1109/FDL.2008.4641444
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subjects Analytical models
Biological system modeling
Design methodology
Embedded system
Libraries
Modeling
Unified modeling language
title Scenario-based validation of embedded systems
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