Enhanced performance Zero Crossing DPLL with linearized phase detector

This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range compared to the c...

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Bibliographic Details
Main Authors: Nasir, Q., Al-Araji, S.R.
Format: Conference Proceeding
Language:English
Subjects:
Detectors
digital phase locked loops
Digital signal processing
Equations
Frequency shift keying
Gain
non-uniform sampling
Phase locked loops
Steady-state
zero crossing DPLL
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Description
Summary:This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS320C6416 DSP development kit.
DOI:10.1109/ISTEL.2008.4651274