Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation

A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region....

Full description

Saved in:
Bibliographic Details
Main Authors: Furuhashi, H., Shino, T., Ohsawa, T., Matsuoka, F., Higashi, T., Minami, Y., Nakajima, H., Fujita, K., Fukuda, R., Hamamoto, T., Nitayama, A.
Format: Conference Proceeding
Language:English
Subjects:
Arrays
Fluctuations
International Electron Devices Meeting
Resource description format
Scalability
Semiconductor process modeling
Signal to noise ratio
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 10 16 cm -3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2008.4656281