FPGA implementation of space-time encoders

This paper describes the concept, architecture, development and demonstration of a 4-transmitter, real-time space-time encoder for multiple-input and multiple-output (MIMO) wireless systems. It is implemented on an FPGA chip in the Altera Stratix EP1S25 DSP Development Kit using VHDL. The system can...

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Bibliographic Details
Main Authors: Fadera, G.N.D., Ignacio, L.R.T., Nastor, M.B.R., Urriza, P.I.M., Marciano, J.J.S.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Encoding
Field programmable gate arrays
OFDM
Registers
Synchronization
Timing
Online Access:Request full text
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Summary:This paper describes the concept, architecture, development and demonstration of a 4-transmitter, real-time space-time encoder for multiple-input and multiple-output (MIMO) wireless systems. It is implemented on an FPGA chip in the Altera Stratix EP1S25 DSP Development Kit using VHDL. The system can be configured to use either space-time block coding (STBC) or space-time trellis coding (STTC). It also allows for the use of OFDM to provide frequency diversity and can be reconfigured to use different space-time coding schemes and different modulation schemes including QPSK, 16QAM, and 8PSK. The performance of the different configurations are measured and compared in terms of FPGA utilizations and maximum achievable bit-rate.
DOI:10.1109/ICIAS.2007.4658410