A new systolic array algorithm for a high throughput low cost VLSI implementation of DCT

This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-leng...

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Bibliographic Details
Main Authors: Chiper, D. F., Swamy, M.N.S., Ahmad, O.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Convolution
Convolutional codes
Costs
Discrete cosine transforms
Hardware
Signal processing algorithms
Systolic arrays
Throughput
Very large scale integration
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Summary:This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-length DCT into several cycle convolutions having the same length and similar structures. Using the proposed approach we can efficiently exploit the inherent parallelism thus doubling the throughput without to double the hardware and I/O cost but only slightly increasing them. Moreover, the proposed VLSI implementation preserves all the other advantages of the VLSI algorithms based on circular correlations or cycle convolutions such as modular and regular structures with local interconnection topology..
DOI:10.1109/ICECS.2008.4674897