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A new systolic array algorithm for a high throughput low cost VLSI implementation of DCT
This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-leng...
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| creator | Chiper, D. F. Swamy, M.N.S. Ahmad, O. |
| description | This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-length DCT into several cycle convolutions having the same length and similar structures. Using the proposed approach we can efficiently exploit the inherent parallelism thus doubling the throughput without to double the hardware and I/O cost but only slightly increasing them. Moreover, the proposed VLSI implementation preserves all the other advantages of the VLSI algorithms based on circular correlations or cycle convolutions such as modular and regular structures with local interconnection topology.. |
| doi_str_mv | 10.1109/ICECS.2008.4674897 |
| format | conference_proceeding |
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F. ; Swamy, M.N.S. ; Ahmad, O.</creator><creatorcontrib>Chiper, D. F. ; Swamy, M.N.S. ; Ahmad, O.</creatorcontrib><description>This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-length DCT into several cycle convolutions having the same length and similar structures. Using the proposed approach we can efficiently exploit the inherent parallelism thus doubling the throughput without to double the hardware and I/O cost but only slightly increasing them. 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Moreover, the proposed VLSI implementation preserves all the other advantages of the VLSI algorithms based on circular correlations or cycle convolutions such as modular and regular structures with local interconnection topology..</description><subject>Algorithm design and analysis</subject><subject>Convolution</subject><subject>Convolutional codes</subject><subject>Costs</subject><subject>Discrete cosine transforms</subject><subject>Hardware</subject><subject>Signal processing algorithms</subject><subject>Systolic arrays</subject><subject>Throughput</subject><subject>Very large scale integration</subject><isbn>1424421810</isbn><isbn>9781424421817</isbn><isbn>1424421829</isbn><isbn>9781424421824</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpFkM1KAzEUhSNS0Na-gG7uC7Te_MwkWZax1kLBRQdxVzLTpBOZaUompczbq1jwbA4fHL7FIeSR4pxS1M_rYlls5wxRzUUuhdLyhoypYEIwqpi-_QeKIzL-HWqkVOIdmfb9F_5EZFzm6p58LuBoL9APfQqtr8HEaAYw7SFEn5oOXIhgoPGHBlITw_nQnM4J2nCBOvQJPjbbNfju1NrOHpNJPhwhOHgpygcycqbt7fTaE1K-LsvibbZ5X62LxWbmNaZZjVoazLnl1KGtpUJGK8GlE5mknFVSZBUzzli3p3lVK2qRG723TORZZqXiE_L0p_XW2t0p-s7EYXd9hX8DnE9T0Q</recordid><startdate>200808</startdate><enddate>200808</enddate><creator>Chiper, D. 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F. ; Swamy, M.N.S. ; Ahmad, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-c097a063e31f0ec78021b437f457132b745b2afaefd16bc81e03a9de24655e783</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Algorithm design and analysis</topic><topic>Convolution</topic><topic>Convolutional codes</topic><topic>Costs</topic><topic>Discrete cosine transforms</topic><topic>Hardware</topic><topic>Signal processing algorithms</topic><topic>Systolic arrays</topic><topic>Throughput</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Chiper, D. F.</creatorcontrib><creatorcontrib>Swamy, M.N.S.</creatorcontrib><creatorcontrib>Ahmad, O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEL</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chiper, D. F.</au><au>Swamy, M.N.S.</au><au>Ahmad, O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new systolic array algorithm for a high throughput low cost VLSI implementation of DCT</atitle><btitle>2008 15th IEEE International Conference on Electronics, Circuits and Systems</btitle><stitle>ICECS</stitle><date>2008-08</date><risdate>2008</risdate><spage>490</spage><epage>493</epage><pages>490-493</pages><isbn>1424421810</isbn><isbn>9781424421817</isbn><eisbn>1424421829</eisbn><eisbn>9781424421824</eisbn><abstract>This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-length DCT into several cycle convolutions having the same length and similar structures. Using the proposed approach we can efficiently exploit the inherent parallelism thus doubling the throughput without to double the hardware and I/O cost but only slightly increasing them. Moreover, the proposed VLSI implementation preserves all the other advantages of the VLSI algorithms based on circular correlations or cycle convolutions such as modular and regular structures with local interconnection topology..</abstract><pub>IEEE</pub><doi>10.1109/ICECS.2008.4674897</doi><tpages>4</tpages></addata></record> |
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| identifier | ISBN: 1424421810 |
| ispartof | 2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008, p.490-493 |
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| language | eng |
| recordid | cdi_ieee_primary_4674897 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Convolution Convolutional codes Costs Discrete cosine transforms Hardware Signal processing algorithms Systolic arrays Throughput Very large scale integration |
| title | A new systolic array algorithm for a high throughput low cost VLSI implementation of DCT |
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