On-chip clock network using interconnected and coupled ring oscillators

All synchronous systems use a clock distribution network covering a large section of the integrated circuit and handling the fastest frequencies of the device. In this work, the performance of interconnected and coupled ring oscillator arrays working as clock distribution networks is analyzed. The u...

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Bibliographic Details
Main Authors: Salim Maza, Manuel, Gonzalez Diaz, Oscar, Linares Aranda, Monico
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Coupling circuits
Fabrication
Frequency
Integrated circuit interconnections
Network-on-a-chip
Power system interconnection
Ring oscillators
Robustness
Topology
Online Access:Request full text
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Description
Summary:All synchronous systems use a clock distribution network covering a large section of the integrated circuit and handling the fastest frequencies of the device. In this work, the performance of interconnected and coupled ring oscillator arrays working as clock distribution networks is analyzed. The use of interconnected three-delay stages rings are proposed even for chip lengths from 4 to 24 mm. Typical 3.3 V AMS 0.35 mum CMOS N-well process parameters were used for the design and fabrication. Experimental results of 16 non-expanded and expanded interconnected ring oscillators agree with simulation.
DOI:10.1109/ICECS.2008.4674904